Programmed logic arrays have been used to execute instructions in computer systems such as, for example, in U.S. Pat. No. 3,949,370, Ser. No. 477,053, "Programmable Logic Array Control Section for Data Processing System", G. F. Reyling, Jr. et al., issued Apr. 6, 1976; U.S. Pat. No. 3,962,683, Ser. No. 394,361, "CPU Programmable Control System", M. Brown et al., issued June 8, 1976; and U.S. Pat. No. 4,074,351, Ser. No. 771,498, "Variable Function Programmed Calculator", G. W. Boone et al., issued Feb. 14, 1978. The PLA's in these patents are arranged on two levels, one PLA generating an instruction or address and all other PLA's responding thereto with the execution of a subroutine on a level lower than that of the first PLA. In effect, the PLA's in each of the aforementioned patents provide the CPU sequencing control. More generally, sequence processing also has been accomplished broadly by means of a module consisting of a PLA coupled with a memory, as shown in U.S. Pat. No. 3,983,538, Ser. No. 465,783, "Universal LSI Array Logic Modules with Integral Storage Array and Variable Autonomous Sequencing", J. W. Jones, issued Sept. 28, 1976. The module is configured to operate autonomously as a selectively programmed miniprocessor with distinctively specialized or personalized operation capabilities and repertoire. Although the combination of PLA and memory is a high performance emulator, it suffers the drawback of higher cost, relative to the present invention, because the PLA required is relatively larger. The combination of PLA and microprocessor in accordance with the present invention, on the other hand, enjoys a cost advantage in that the PLA required is relatively smaller and the microprocessor utilized is commercially available at low cost.